More memory is being embedded into system-on-chip (“SOC”) devices in order to provide increasing functionality. Many SOC devices have more than 50% of their area devoted to embedded memories. Ensuring these memories are valid and operating correctly is of the upmost importance for producing SOC devices. In addition, as memory content increases, those memories become more susceptible to defects and variations in the chip parametric as technology feature sizes decrease. Thus, the memories of the SOC devices require methods and systems for thorough and efficient testing, repairing, and diagnosis.
A memory built-in self test (“BIST”) has emerged as the most effective way to test, repair, and diagnose the numerous memory instances found in modern SOC devices. Typical BIST circuits are coupled to each type of embedded memory of the SOC devices. Thus, if a SOC device has a single port memory device, a ternary content addressable memory (“TCAM”) device, and a non-single port memory device, a separate BIST controller is coupled to each type of memory device. This leads to inefficient use of the SOC area and additional complexity when testing the multiple memory types of the SOC device. Therefore, it is desirable for providing a BIST architecture that provides additional features for improving the quality of testing of a SOC device while minimizing BIST circuit area overhead.